1. Field of the Invention
The present invention relates to a semiconductor storage apparatus and a manufacturing method thereof, particularly but not limited to a flash memory having a self-aligned silicide (SALICIDE) structure and a manufacturing method of the flash memory. The present application is based on Japanese Patent Application No. 154561/2000, which is incorporated herein by reference
2. Background
FIG. 1 is an equivalent circuit diagram of a flash memory cell array. As shown in FIG. 1, a flash memory 1 includes a plurality of memory cells 1a, X decoder 1b, and Y decoder and sense amplifier 1c. 
A gate electrode of a transistor constituting each memory cell 1a is connected to a word line WL (only WL1 to WL4 are shown), a drain side of the transistor is connected to a bit line BL (only BL1 to BL3 are shown) via a drain contact 2, and a source side of the transistor is connected to a source line SL via a source contact 3.
Moreover, each word line WL is connected to the X decoder 1b, each bit line BL is connected to the Y decoder and sense amplifier 1c, each memory cell 1a is selectively designated by the word line WL, and information is inputted/outputted via the bit line BL.
FIG. 2 is an explanatory plan view showing a part of the memory cells of FIG. 1. As shown in FIG. 2, the transistors constituting the memory cell 1a are disposed on opposite sides via the drain contact 2. The drain contact 2 is disposed in a drain diffusion layer 4a, and a source diffusion layer 4b is disposed between the word lines WL adjacent to each other.
FIGS. 3A to 3B are sectional views showing a portion of a manufacturing process of the flash memory. The left figures of FIGS. 3A to 3E are views taken along lines A—A of FIG. 2. The right figures of FIGS. 3A to 3E are views taken along lines B—B of FIG. 2. As shown in FIG. 3A, when the flash memory 1 is manufactured, first an isolation oxide film 5a and a tunnel oxide film 5b are formed on a P-type silicon substrate 5, further a floating gate 5c, interpoly insulating film 5d, and control gate 5e are successively stacked, and a transistor 6 is formed on the silicon substrate 5.
Subsequently, as shown in FIG. 3B, a photo-resist 7 is patterned so as to open only a source portion, then the isolation oxide film 5a is etched by using the photo-resist 7 as a mask. Subsequently, as shown in FIG. 3C, the source diffusion layer 4b common to two adjacent transistors 6, and then the drain diffusion layer 4a are formed by ion implantation.
A structure formed by the aforementioned process is called a self-aligned source structure. In the structure it is unnecessary to dispose the source contact for each memory cell, an alignment margin, and the like are unnecessary, and a memory cell size can be reduced.
Subsequently, as shown in FIG. 3D, side walls 8 are formed on both side surfaces of each transistor 6, and subsequently, as shown in FIG. 3E, the respective exposed surfaces of the drain diffusion layer 4a, source diffusion layer 4b and control gate 5c are covered with a silicide film 9.
The silicide film 9 can be formed by alloy forming reaction of a refractory metal film with a substrate, and, for example, a known self-aligned silicide (SALICIDE) process using titanium (Ti) can be used to form the silicide film.
The SALICIDE process, for example, includes: forming the gate electrode and side wall; subsequently implanting impurities to form the source/drain diffusion layers and annealing the layers; subsequently sputtering titanium, for example, by 50 nm; annealing the layers at about 700° C. to perform silicidation; and removing non-reacted titanium. Thereby, the silicide film 9 on the drain diffusion layer 4a, source diffusion layer 4b and control gate 5c can easily be formed in a self-aligned manner (see Japanese Patent Application Laid-Open No. 330453/1996).
To form the silicide film on the diffusion layer and gate surface in this manner is essential, especially in a random logic large scale integrated (LSI) circuit, in order to reduce parasitic resistance and realize a fine and high performance device.
However, since the source area of the memory cell 1a is held between the gates and is very narrow, a sputtering film cannot easily enter the area, and silicidation tends to be insufficient. This brings about a dispersion of resistance. Moreover, when the isolation oxide film 5a and tunnel oxide film 5b are etched, a step portion is generated, as shown in FIG. 3B. Therefore, since a step portion L is covered with the silicide film 9, as shown in FIG. 3E, the silicide film 9 is easily disconnected in the step portion L, and the dispersion of resistance is caused by disconnection.
An object of the present invention is to provide a semiconductor storage apparatus and a manufacturing method thereof in which a memory cell source area is not silicided, dispersion of resistance caused by insufficient silicidation is therefore eliminated, and dispersion of resistance caused by disconnection of a silicide film in the step portion of a self-aligned source structure is also prevented.